基于导频的储存环束流位置测量处理器研制

稳定的束流轨道对于同步辐射光源的性能至关重要，规划中的合肥先进光源是第四代衍射极限储存环，其亚微米级的束流轨道稳定度需要束流位置测量精度达到100 nm级别。本文基于国产化芯片，研制了带有导频补偿机制的束流位置测量处理器，主要包括导频模块、模拟前端模块、数字处理模块和嵌入式工控模块。输入信号经过导频模块和模拟前端模块调理，在数字处理模块通过带通欠采样原理实现模数转换，数字信号在现场可编程门阵列（FPGA）内经过下变频、滤波抽取、坐标旋转数字计算（CORDIC）模块以及差比和算法等处理后获得束流位置信息，嵌入式工控模块实时传输束流位置信号，与加速器控制系统通信。目前设计的束流位置处理器完成了实验室离线测试和束流测试，测试结果表明，当输入信号幅度在-55～5 dBm范围时，束流位置测量处理器的快获取数据（FA data）和慢获取数据（SA data）分辨率分别好于120 nm和70 nm，满足设计要求。

Development of Pilot-tone Based BPM Processor of Storage Ring

Beam orbit stability is vital for the synchrotron radiation light source. Hefei Advanced Light Facility (HALF), the fourth generation diffraction limit storage ring now under preliminary research with sub micron beam orbit stability, requires a beam position monitor (BPM) system with accuracy better than 100 nm. In this paper, a BPM processor with pilot tone was developed using domestic chips, which is composed of the pilot tone module, the analog front end module, the digital processing module and the embedded control module. The input signals from BPM detector were adjusted in pilot tone module and analog front end module, digitalized in digital processing module by band pass sampling principle, and the digital signals were processed in FPGA (field programmable gata array) to obtain turn by turn data, fast acquisition data (FA data) at a 10 kHz rate, and slow acquisition data (SA data) at a 10 Hz rate. The embedded control module transmitted the beam position information in real time and communicated with the accelerator control system. Thermal drifts of the channels and variations of the cables frequency response (due to changes in temperature or humidity) could introduce uncontrolled fluctuations in the position calculated. To enhance long term stability of the BPM processor, a low phase noise pilot tone was added to the beam signal as a reference to eliminate the effect of gain drifts of the individual channel on position calculation. The analog front end was customized with adjustable gain to increase the dynamic range of the system, and composed of four identical radio frequency (RF) channels, each with several amplifiers, attenuators and filters to adjust the signals for ADC sampling. All beam position calculations were performed in the digital domain. The band pass sampling technique was applied to convert narrow band RF signals into intermediate frequency (IF) digital signals. And then the IF signals were converted to the base band in phase and quadrature phase (IQ) data through the digital down conversion method. CIC (cascaded integrator comb) and FIR (finite impulse response) decimation filters were used to avoid high component signal aliasing and decimate the IQ data rate. CORDIC (coordinated rotation digital computer) module was implemented in pipeline structure to calculate the signal amplitudes from IQ data. With four BPM signal amplitudes, the beam position could be obtained by the difference over sum algorithm. These digital signal processing algorithms were integrated on one FPGA. At present, the laboratory offline tests and the beam tests of the designed beam position processor were carried out. The offline tests demonstrate the effectiveness of pilot tone in compensating for external changes and improving the long term stability. The test results indicate that the resolutions of the FA data and SA data are better than 120 nm and 70 nm respectively with the input amplitudes ranging from -55 dBm to 5 dBm, which meet the design requirements.