| 嵌入式数字锁相环的设计与实现 |
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| 引用本文： | 单长虹,孟宪元.嵌入式数字锁相环的设计与实现[J].计算机仿真,2003,20(6):93-95,42. |
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| 作者姓名： | 单长虹 孟宪元 |
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| 作者单位： | 1. 南华大学电气工程学院,湖南,衡阳,421001
2. 清华大学电子工程系,北京,100084 |
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| 摘 要： | 介绍了应用VHDL技术设计嵌入式数字锁相环的方法，给出了系统仿真结果，并用可编程逻辑器件FPGA予以实现。该锁相环能够实现正交锁定或反相锁定，并具有控制灵活、锁定频率高和系统稳定性好等特点。
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| 关 键 词： | 嵌入式数字锁相环 设计 系统仿真 可编程逻辑器件 系统芯片 |
| 文章编号： | 1006-9348(2003)06-0093-03 |
The Design and Implementation of Embedded Digital Phase-locked Loops |
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| SHAN Chang-hong,MENG Xian-yuan.The Design and Implementation of Embedded Digital Phase-locked Loops[J].Computer Simulation,2003,20(6):93-95,42. |
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| Authors: | SHAN Chang-hong MENG Xian-yuan |
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| Affiliation: | SHAN Chang-hong1,MENG Xian-yuan2 |
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| Abstract: | The design of embedded digital phase-locked loops with VHDL is introduced , and simulation result is given. The DPLL is implemented with FPGA . It can realize quadrature or reversed phaselocked. The DPLL is more agile in control , higher in locking frequency and better in stability. |
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| Keywords: | DPLL SOC FPGA |
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