| 改进的抽取滤波器设计 |
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| 引用本文： | 潘桃莉,谢光忠,周云,蒋亚东. 改进的抽取滤波器设计[J]. 微处理机, 2011, 32(1): 7-10. DOI: 10.3969/j.issn.1002-2279.2011.01.003 |
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| 作者姓名： | 潘桃莉 谢光忠 周云 蒋亚东 |
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| 作者单位： | 电子科技大学光电信息学院,电子薄膜与集成器件国家重点实验室,成都,610054 |
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| 摘 要： | 在Sigma-Delta ADC芯片中,数字抽取滤波器电路占据了大部分面积。所设计的改进型Hogenauer CIC滤波器,将梳状部分进行优化,采用控制单元、加法器和寄存器代替传统Hogenauer CIC滤波器中的差分器,从而减小数字电路的面积。一个采用这种结构的4阶32倍降采样数字滤波器在Stratix Ⅱ系列2S30 FPGA芯片中实现。经过测试,耗费的硬件资源比传统Hogenauer结构滤波器减少11%。
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| 关 键 词： | Hogenauer滤波器 抽取滤波器 现场可编程门阵列 |
Design of Improved Decimation Filter |
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| PAN Tao-li,XIE Guang-zhong,ZHOU Yun,JIANG Ya-dong. Design of Improved Decimation Filter[J]. Microprocessors, 2011, 32(1): 7-10. DOI: 10.3969/j.issn.1002-2279.2011.01.003 |
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| Authors: | PAN Tao-li XIE Guang-zhong ZHOU Yun JIANG Ya-dong |
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| Affiliation: | PAN Tao-li,XIE Guang-zhong,ZHOU Yun,JIANG Ya-dong(School of Optoelectronic Information,University of Electronic Science and Technology of China,State Key Laboratory of Electronic Thin Films and Integrated Devices,Chengdu 620054,China) |
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| Abstract: | Digital circuit of decimation filter occupies most of chip area in Sigma-Delta ADC.In this paper,an improved Hogenauer CIC filter is designed.A control unit,an adder and some registers are used to replace multiple of adders in traditional Hogenauer CIC filter,in order to optimize the comb part of decimation filter and reduce digital circuit area.A fourth order digital filter employing such method with downsampling rate of 32 is designed and realized in Stratix II set 2S30 FPGA chip.As a result of practice,i... |
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| Keywords: | Hogenauer Filter Decimation Filter FPGA |
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