| Ultra2 SCSI PCB设计中的阻抗匹配问题 |
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| 引用本文： | 赵忠文,曾峦,王建成.Ultra2 SCSI PCB设计中的阻抗匹配问题[J].装备指挥技术学院学报,2000,11(4). |
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| 作者姓名： | 赵忠文 曾峦 王建成 |
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| 作者单位： | 装备指挥技术学院测量控制系 |
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| 摘 要： | 在高速逻辑设计中,需要考虑避免出现振铃、串扰等传输线现象.就此,详细讨论了在Ultra2 SCSI单端和差分模式兼容下PCB的两种输出阻抗及其与连接电缆的阻抗匹配问题的解决方法,简单介绍了在这样的高速逻辑系统中,PCB设计通常要考虑的一些其它问题.
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| 关 键 词： | Ultra2SCSI Fast—40 PCB 高速逻辑设计 |
Design a Universal Backplane for UItra2 SCSI |
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| Zhao Zhongwen Zeng Luan Wang Jiancheng.Design a Universal Backplane for UItra2 SCSI[J].Journal of the Academy of Equipment Command & Technology,2000,11(4). |
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| Authors: | Zhao Zhongwen Zeng Luan Wang Jiancheng |
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| Affiliation: | Department of Measurement and Control. Institute of Command and Technology of Equipment |
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| Abstract: | In design for high-speed logic, we should dispose the appearance of transmission line. This paper goes into particulars that a universal backplane for Ultra2 SCSI needs to have a differential output impedance that is comparable to the cable differential and single-ended impedance. And some general guidelines for laying out the PCB are presented. |
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| Keywords: | Ultra2 SCSI Fast-40 PCB high-speed logic design |
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