| 用分解真值表法实现用中规模集成电路构成组合电路的设计 |
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| 引用本文： | 周德新,钱培怡.用分解真值表法实现用中规模集成电路构成组合电路的设计[J].辽宁石油化工大学学报,1999(Z1). |
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| 作者姓名： | 周德新 钱培怡 |
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| 作者单位： | 抚顺石油学院自动化系!辽宁抚顺113001 |
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| 摘 要： | 在用中规模集成电路构成组合逻辑电路的设计中，把一个比较庞大的真值表，分解成若干个简单变量关系较少的真值表，通过对分解的真值表的分析，可以很方便地得出设计要求的结论。
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| 关 键 词： | 集成电路 真值表 组合逻辑电路 |
A Design of Combined Logic Circuit Constructed with Middle Scale Integrated Circuits Though Dividing the True Table |
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| Zhou Dexin,Qian Peiyi.A Design of Combined Logic Circuit Constructed with Middle Scale Integrated Circuits Though Dividing the True Table[J].Journal of Liaoning University of Petroleum & Chemical Technology,1999(Z1). |
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| Authors: | Zhou Dexin Qian Peiyi |
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| Abstract: | In the designing of a logic circuit constructed with middle scale integrated circuit, a major true table is divided into several simple true tables with less variables. The required results are gained easily and quickly through analyzing the divided true tables. |
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| Keywords: | Integrated Circuit Truetable |
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