| 小尺寸MOS晶体管的漏致势垒降低效应建模 |
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| 引用本文： | 陈磊,孙玲玲,刘军.小尺寸MOS晶体管的漏致势垒降低效应建模[J].杭州电子科技大学学报,2010,30(3):1-4. |
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| 作者姓名： | 陈磊 孙玲玲 刘军 |
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| 作者单位： | 杭州电子科技大学电子信息学院,浙江,杭州,310018 |
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| 基金项目： | 国家自然科学基金资助项目 |
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| 摘 要： | 该文针对PSP模型中漏致势垒降低效应建模纯经验性的缺点,通过求解二维泊松方程得到漏致势垒降低效应引起阈值电压漂移的解析解,并将其应用于32nm晶体管的直流I-V曲线拟合,结果显示此模型有很好的拟合精度。
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| 关 键 词： | 表面势 漏致势垒降低 阈值电压漂移 |
DIBL Modeling in Small-sized MOSFETs |
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| CHEN Lei,SUN Ling-ling,LIU Jun.DIBL Modeling in Small-sized MOSFETs[J].Journal of Hangzhou Dianzi University,2010,30(3):1-4. |
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| Authors: | CHEN Lei SUN Ling-ling LIU Jun |
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| Affiliation: | CHEN Lei,SUN Ling-ling,LIU Jun(Key Laboratory of RF Circuit and System,Ministry of Education,Hangzhou Dianzi University,Hangzhou Zhejiang 310018,China) |
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| Abstract: | An analytical solution of two-dimensional Poisson's equation is derived to calculate the DIBL effect.This model predicts an exponential dependence on channel length,a linear dependence on drain bias.Without any fitting parameters,the good agreement between the simulated results and measured data reported in a published paper proves that this model is well applicable in deep sub-micron range,even in nanoscale. |
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| Keywords: | surface potential drain induced barrier lowing threshold voltage roll-off |
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