A novel open-loop high-speed CMOS sample-and-hold |
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Authors: | Morteza Khayrollah Abdollah |
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Affiliation: | aMicroelectronics Research Laboratory, Urmia University, Urmia, West Azerbaijan 53139, Iran |
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Abstract: | A new open-loop high-speed CMOS sample-and-hold is presented. Based on new method for further reduction of voltage-dependent charge injection, a new CMOS sample-and-hold was designed. Simulation results confirm the effectiveness of this method. Over 10 dB improvement in signal-to-noise ratio, compared to the signal-to-noise ratio of conventional bottom plate sampling S/Hs was achieved with this method. A comparison between newly designed S/H and the bottom-plate sampling S/H is presented. |
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Keywords: | Sample and hold ADC Charge injection Linearity |
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