Narrow-band low-noise amplifier synthesis for high-performance system-on-chip design

In this paper, we present a systematic synthesis methodology for fully integrated narrow-band CMOS low-noise amplifiers (LNAs) in high-performance system-on-chip (SoC) designs. The methodology is based on deterministic gradient-based numerical nonlinear optimization and the normal boundary intersection (NBI) method for Pareto optimization. We simultaneously optimize transistor widths, bias voltages, and input and output matching network passive components, which yields integrated inductor values that are more than one order of magnitude less than those generated by several existing equation-based LNA design techniques. By generating significantly smaller inductor values, we enable the SoC integration of the complete LNA. When the synthesized LNAs are characterized using circuit-level simulation, our methodology yields up to 35% and 58% improvement in noise figure and gain, respectively.