基于FPGA的同步计数器的优化结构分析

在数字信号处理中，同步计数器是一种非常重要的器件，在很多场所会用到。在基于现场可编程门阵列(FPGA)器件的开发过程中，人们往往不会注意所用到的同步计数器内部的具体设计。本文从资源利用率和速率两个方面，对FPGA开发综合工具自动综合出来的同步计数器进行分析，并且提出一种结构优化的同步计数器，并将两种同步计数器进行对比，得出了两者的优缺点及适用的场合。

Optimization Structure Analysis of Synchronous Counter Based on FPGA

In the digital signal processing,the synchronous counter is a very important device,it is used in many fields.In the development of FPGA,the inside specific design of the synchronous counter is not paid attention to.In this paper,the synchronous counter of the auto-matic synthesis of FPGA development tools is analyzed in two aspects of the resource utilization and the rate,and a kind of synchronous counter with optimized structure is proposed.Finally,the two kinds of synchronous counter are compared,and the advantages and disad-vantages are obtained.