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存储芯片层次化分割P/G网等效电阻求解算法
引用本文:竺红卫,严晓浪,孙玲玲,马琪. 存储芯片层次化分割P/G网等效电阻求解算法[J]. 电路与系统学报, 2001, 6(4): 7-10
作者姓名:竺红卫  严晓浪  孙玲玲  马琪
作者单位:1. 浙江大学,信息与电子工程系,浙江,杭州,310012
2. 杭州电子工业学院,CAD所,浙江,杭州,310037
基金项目:浙江省自然科学重点基金资助项目
摘    要:由于存储芯片版图P/G网规模的巨大,对于计算电阻网络中节点间等效电阻问题,直接利用常规线性方程组求解算法无法同时满足内存空间与运行时间上的限制。针对版图线网网络关联密集度不均衡的特点,本文提出了一种层次化网络分割算法,将全局网络按层次分割成可求解子网,并利用等效子网算法实现多观测点快速计算。

关 键 词:等效电阻 存储芯片 层次化分割 VLSI P/G网 集成电路
文章编号:1007-0249(2001)04-07-05

A Hierarchy Partition Algorithm for Calculating the Equivalent Resistance in Memory Chip P/G Network
ZHU Hong-wei,YAN Xiao-lang,SUN Ling-ling,MA Qi. A Hierarchy Partition Algorithm for Calculating the Equivalent Resistance in Memory Chip P/G Network[J]. Journal of Circuits and Systems, 2001, 6(4): 7-10
Authors:ZHU Hong-wei  YAN Xiao-lang  SUN Ling-ling  MA Qi
Affiliation:ZHU Hong-wei1,YAN Xiao-lang1,SUN Ling-ling2,MA Qi2
Abstract:Because of the large scale of the P/G routing network in the memory chip layout, general linear equation group resolving algorithms for calculating the equivalent resistance between the nodes cannot satisfy the restrict of both memory space and running time simultaneously. Referring to the characteristic of different density among the nodes in the routing network, an algorithm of loop network partition is presented, in which the whole network is hierarchically divided into several resolvable sub-networks, and an fast algorithm for calculating multiple detected nodes is also devised.
Keywords:
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