Effects of hot carrier induced interface state generation insubmicron LDD MOSFET's |
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| Authors: | Tahui Wang Chimoon Huang Chou P.C. Chung S.S.-S. Tse-En Chang |
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| Affiliation: | Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu; |
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| Abstract: | A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 μm LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at Vg ≃0.5 Vd in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states |
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