一种基于开关型运放和双向循环移位DWA的0.9V Delta-Sigma模数转换器

This paper presents a low-power high-precision switched-opamp(SO)-based delta-sigma(△Σ) analog-to -digital converter(ADC).The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging (DCS-DWA) technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit(FOM) of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.

A 0.9-V switched-opamp-based delta-sigma ADC with dual cycle shift DWA