| F-N应力下SOI n-MOSFETs性能退化与栅控二极管产生-复合（G-R）电流的对应关系 |
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| 引用本文： | 何进,马晨月,王昊,陈旭,张晨飞,林信南,张兴. F-N应力下SOI n-MOSFETs性能退化与栅控二极管产生-复合（G-R）电流的对应关系[J]. 半导体学报, 2009, 30(12): 124004-3 |
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| 作者姓名： | 何进 马晨月 王昊 陈旭 张晨飞 林信南 张兴 |
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| 作者单位： | Key Laboratory of Integrated Microsystems;School of Computer & Information Engineering;Peking University Shenzhen Graduate School;TSRC;Institute of Microelectronics;School of Electronic Engineering and Computer Science;Peking University; |
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| 摘 要： | 本文验证了F-N应力导致的SOI n- MOSFET器件性能退化与栅控二极管的产生-复合（G-R）电流的对应关系。F-N应力导致的界面态增加会导致SOI-MOSFET结构的栅控二极管的产生-复合（G-R）电流增大，以及MOSFET饱和漏端电流，亚阈斜率等器件特性退化。通过一系列的SOI-MOSFET栅控二极管和直流特性测试，实验观察到饱和漏端电流的线性退化和阈值电压的线性增加，亚阈摆幅的类线性上升以及相应的跨导退化。理论和实验证明栅控二极管是一种很有效的监控SOI-MOSFET退化的方法。
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| 关 键 词： | MOSFET退化，F-N应力，界面陷阱，栅控二极管方法，SOI技术 |
| 修稿时间： | 2009-08-02 |
Clear correspondence between gated-diode R-G current and performance degradation of SOI n-MOSFETs after F--N stress tests |
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| He Jin,Ma Chenyue,Wang Hao,Chen Xu,Zhang Chenfei,Lin Xinnan and Zhang Xing. Clear correspondence between gated-diode R-G current and performance degradation of SOI n-MOSFETs after F--N stress tests[J]. Chinese Journal of Semiconductors, 2009, 30(12): 124004-3 |
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| Authors: | He Jin Ma Chenyue Wang Hao Chen Xu Zhang Chenfei Lin Xinnan Zhang Xing |
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| Affiliation: | Key Laboratory of Integrated Microsystems, School of Computer & Information Engineering, Peking University Shenzhen Graduate School, Shenzhen 518055, China; TSRC, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking;TSRC, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871, China;TSRC, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871, China;TSRC, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871, China;TSRC, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871, China;Key Laboratory of Integrated Microsystems, School of Computer & Information Engineering, Peking University Shenzhen Graduate School, Shenzhen 518055, China;TSRC, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871, China |
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| Abstract: | |
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| Keywords: | MOSFET degradation F-N stress interface traps gated-diode method SOI technology |
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