| 一种高速低功耗动态比较器设计 |
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| 引用本文： | 彭宣霖,李航标,陈剑洛,王新宇,付松林,罗萍. 一种高速低功耗动态比较器设计[J]. 微电子学, 2014, 0(5): 601-605 |
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| 作者姓名： | 彭宣霖 李航标 陈剑洛 王新宇 付松林 罗萍 |
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| 作者单位： | 电子科技大学 电子薄膜与集成器件国家重点实验室, 成都 610054;电子科技大学 电子薄膜与集成器件国家重点实验室, 成都 610054;电子科技大学 电子薄膜与集成器件国家重点实验室, 成都 610054;电子科技大学 电子薄膜与集成器件国家重点实验室, 成都 610054;电子科技大学 电子薄膜与集成器件国家重点实验室, 成都 610054;电子科技大学 电子薄膜与集成器件国家重点实验室, 成都 610054 |
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| 摘 要： | 提出了一种应用于最小能量追踪系统的改进型高速低功耗动态比较器。通过在锁存比较器中引入额外的正反馈,使得动态比较器具有响应速度更快、功耗更小的优点,同时电路规模与版图面积基本保持不变。基于65 nm CMOS工艺的HSPICE仿真显示,所提出的动态比较器在输入电压差为1 mV时,传输延迟仅为1.82 ns,较未改进之前的3.57 ns,传输延迟大幅度减小。
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| 关 键 词： | 动态比较器 高速 响应速度 传输延迟 |
| 收稿时间： | 2013-07-04 |
Design of a High Speed Low Power Dynamic Comparator |
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| PENG Xuanlin,LI Hangbiao,CHEN Jianluo,WANG Xinyu,FU Songlin and LUO Ping. Design of a High Speed Low Power Dynamic Comparator[J]. Microelectronics, 2014, 0(5): 601-605 |
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| Authors: | PENG Xuanlin LI Hangbiao CHEN Jianluo WANG Xinyu FU Songlin LUO Ping |
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| Affiliation: | State Key Lab of Electronic Thin Films and Integr. Dev., Univ. of Electronic Science and Technology of China, Chengdu 610054, P. R. China;State Key Lab of Electronic Thin Films and Integr. Dev., Univ. of Electronic Science and Technology of China, Chengdu 610054, P. R. China;State Key Lab of Electronic Thin Films and Integr. Dev., Univ. of Electronic Science and Technology of China, Chengdu 610054, P. R. China;State Key Lab of Electronic Thin Films and Integr. Dev., Univ. of Electronic Science and Technology of China, Chengdu 610054, P. R. China;State Key Lab of Electronic Thin Films and Integr. Dev., Univ. of Electronic Science and Technology of China, Chengdu 610054, P. R. China;State Key Lab of Electronic Thin Films and Integr. Dev., Univ. of Electronic Science and Technology of China, Chengdu 610054, P. R. China |
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| Abstract: | An improved high speed low-power dynamic comparator was proposed, which was used in minimum energy point tracking (MEPT) system. By introducing an extra positive feedback to the latch comparator, the proposed dynamic comparator had advantages of fast transient response and low power consumption. Meantime, the on-chip area was almost unchanged. Based on a 65 nm CMOS process, simulation results showed that the transport delay of the proposed dynamic comparator was just 1.82 ns when the input difference voltage was 1 mV, which was an exciting improvement compared with 3.57 ns transport delay of the conventional structure. |
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