AC-Boosting Frequency Compensation with Double Pole-Zero Cancellation for Multistage Amplifiers |
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| Authors: | M T Tan P K Chan C K Lam C W Ng |
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| Affiliation: | (1) Faculty of Electrical Engineering Mathematics and Computer Sciences (EEMCS), Delft University of Technology, Mekelweg 4, 2628 CD Delft, Netherlands |
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| Abstract: | In this paper, we present an AC-boosting compensation topology with double pole-zero cancellation (ACBC-DPZ) for a multistage
amplifier driving a very large capacitive load. The proposed technique modifies the original AC-boosting compensation (ACBC)
topology to increase the power-bandwidth efficiency and reduce the size for the output power transistor and compensation capacitor.
Simulation results show that the ACBC-DPZ amplifier using a CSM 0.18 μm CMOS process can achieve a unity gain bandwidth of
14 MHz and an average slew rate of 3.88 V/μs at 1500 pF load. The amplifier dissipates 2.55 mW at a 1.8 V supply. |
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