| 一种MPEG2视频解码器的系统设计 |
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| 引用本文： | 陈旭昀,郑金山,周汀,章倩苓. 一种MPEG2视频解码器的系统设计[J]. 固体电子学研究与进展, 2000, 20(1): 60-65 |
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| 作者姓名： | 陈旭昀 郑金山 周汀 章倩苓 |
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| 作者单位： | 复旦大学专用集成电路与系统国家实验室!上海，200433，复旦大学专用集成电路与系统国家实验室!上海，200433，复旦大学专用集成电路与系统国家实验室!上海，200433，复旦大学专用集成电路与系统国家实验室!上海，200433 |
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| 摘 要： | 对于设计像 MPEG2视频解码器的复杂系统 ,关键的难点是其系统结构的设计。文中设计了一种适合 VL SI实现的 MPEG2解码器的系统结构。它支持 MPEG2 (MP@ML)码流 ,并且兼容 MPEG1码流。为了设计和优化这个结构 ,采用硬件描述语言 VHDL 设计了系统级的 MPEG2视频解码器。此解码器在 Viewlogic系统中进行了模拟 ,并且对一些码流进行了测试验证。
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| 关 键 词： | 运动图像专家组 视频解码 超大规模集成电路 |
The System Architecture Design of a MPEG2 Video Decoder for VLSI Implementation |
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| Chen Xuyun Zheng Jinshan Zhou Ting Zhang Qianling. The System Architecture Design of a MPEG2 Video Decoder for VLSI Implementation[J]. Research & Progress of Solid State Electronics, 2000, 20(1): 60-65 |
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| Authors: | Chen Xuyun Zheng Jinshan Zhou Ting Zhang Qianling |
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| Abstract: | For complex system like MPEG2 video decoder, the crucial difficulty is its system architecture design. In this paper, a system architecture of MPEG2 video decoder suitable for VLSI implementation is designed. This architecture is specified in MPEG2 main profile at the main level (MP@ML) and is compatible with MPEG1 bitstream. In order to design and optimize this architecture, a system level MPEG2 decoder is developed, which is described by VHDL and simulated in viewlogic environment. Some bitstreams have been tested to show its correctness. |
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| Keywords: | MPEG video decoding VLSI |
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