| IDCT IP核的VLSI结构 |
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| 引用本文： | 饶海潮,郭立,黄征. IDCT IP核的VLSI结构[J]. 微电子学与计算机, 2004, 21(8): 132-134 |
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| 作者姓名： | 饶海潮 郭立 黄征 |
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| 作者单位： | 中国科技大学集成电路与系统实验室,安徽,合肥,230026 |
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| 摘 要： | 摘介绍了一种新型的IDCT IP核的VLSI结构，这种并行结构结合分布式算法和基于存储器的查找表，系统自顶向下分解为模块，设计出一个不需要乘法器的高性能IP核，可以实时处理MPEG2 MP@ML。
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| 关 键 词： | 离散余弦反变换 IP核 乘累加单元 |
| 文章编号： | 1000-7180(2004)08-132-03 |
| 修稿时间： | 2004-01-15 |
Architecture of VLSI for IDCT IP Core |
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| RAO Hai-chao,GUO Li,HUANG Zheng. Architecture of VLSI for IDCT IP Core[J]. Microelectronics & Computer, 2004, 21(8): 132-134 |
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| Authors: | RAO Hai-chao GUO Li HUANG Zheng |
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| Abstract: | This paper introduces a new VLSI architecture for IDCT IP core. The pa rallel architecture combines distributed algorithm and look-up table based memor y. The system is divided into modules from the top to down.. A high performance IP core is designed without multiplier and can process MPEG2 MP@ML in real time . |
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| Keywords: | IDCT IP core MAC unit |
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