| 组合逻辑电路的逻辑级数优化 |
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| 引用本文： | 叶以正 曾献君. 组合逻辑电路的逻辑级数优化[J]. 计算机辅助设计与图形学学报, 1997, 9(1): 46-52 |
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| 作者姓名： | 叶以正 曾献君 |
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| 作者单位： | 哈尔滨工业大学计算机系 |
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| 摘 要： | 本文讨论了基于逻辑级数极化小的布尔孙数因子分解，提出了基于Ｌａｗｌｅｒ分割算法及子逻辑结构变换的组合逻辑电路的逻辑级数优化方法。
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| 关 键 词： | 延迟时间 组合逻辑电路 逻辑级数 |
REDUCING THE LOGIC LEVEL OF THE COMBINATIONAL CIRCUITS |
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| Ye Yizheng,Zeng Xianjun and Zhang Yan. REDUCING THE LOGIC LEVEL OF THE COMBINATIONAL CIRCUITS[J]. Journal of Computer-Aided Design & Computer Graphics, 1997, 9(1): 46-52 |
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| Authors: | Ye Yizheng Zeng Xianjun Zhang Yan |
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| Abstract: | This paper discusses the boolean functions factoring method to minimize the logic level of the combinational circuits and presents an algorithm to reduce the logic level of the combinational circuits based on the Lawler clustering algorithm and the sublogic structural transformations. |
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| Keywords: | optimization function factoring multi level logic synthesis. |
| 本文献已被 CNKI 维普 等数据库收录！ |
