用于低功耗设计和测试的自适应触发器

提出一种触发器结构——自适应触发器，它可以同时降低VLSI电路的工作功耗和扫描测试时的功耗，自适应触发器监视D端和Q端的逻辑电平，当两者的逻辑电平相等时，就会自动把触发器的内部时钟停在逻辑高电平；否则，触发器要跳变时，就会自动地恢复触发器的内部时钟，在触发器的跳变率较低时，自适应触发器能有效地降低触发器的功耗，同DL—DFF和时钟门控相比，自适应触发器具有不需要附加额外电路，并能同时降低电路的工作功耗和扫描测试功耗的优点。

Self-Adaptive D-Flip-Flop for Low Power Design and Test

A new structure D Flip Flop and corresponding scan Flip Flop, namely Self Adaptive D Flip Flop (SA DFF) is proposed to reduce the power consumption of CMOS VLSI in normal operation mode and scan test mode simultaneously SA DFF compares the logic level of D port and Q port, automatically deactivates the internal clock when they are equal, or reactivates the internal clock when they are not equal Under low data transition probability circumstances, the SA DFF consumes less power than a conventional one In comparison with DL DFF and gated clock, the main features of SA DFF are capable of reducing both normal operation and scan test power dissipation without the need of extra pulse generation or glitch elimination circuits