一种基于位交错结构的亚阈值10管SRAM单元

提出了一种基于位交错结构的亚阈值10管SRAM单元,实现了电路在超低电压下能稳定地工作,并降低了电路功耗。采用内在读辅助技术消除了读干扰问题,有效提高了低压下的读稳定性。采用削弱单元反馈环路的写辅助技术,极大提高了写能力。该10管SRAM单元可消除半选干扰问题,提高位交错结构的抗软错误能力。在40 nm CMOS工艺下对电路进行了仿真。结果表明,该10管SRAM单元在低压下具有较高的读稳定性和优异的写能力。在0.4 V工作电压下,该10管SRAM单元的写裕度为传统6管单元的14.55倍。

A Subthreshold 10T SRAM Cell Based on Bit-Interleaving Architecture

A subthreshold 10T SRAM cell based on bit-interleaving architecture was proposed, which could work stably under ultra-low voltage and reduce circuit power consumption. The built-in read assist scheme eliminated the read disturb issue and effectively improved the read stability under low voltage. The write ability was greatly improved by using the write assist technique which weakened the feedback loop of the cell. The 10T SRAM cell could eliminate the half-select disturb and improve the soft error immunity of the bit-interleaving architecture. The circuit was simulated in a 40 nm standard CMOS process. The results indicated that the 10T SRAM cell had high read stability and excellent write ability under low voltage. At 0.4 V supply voltage, the write margin of the 10T SRAM cell was 14.55 times larger than that of the conventional 6T cell.