低抖动时钟产生电路设计

相位噪声和抖动是考量周期信号性能最常用的2个指标。介绍了相位噪声和抖动的概念，详细分析了两者之间的联系，设计了一个低抖动的标频时钟模块，测试结果表明均方根（RMS）周期抖动≤250 fs。

Design of Low-jitter Clock Generation Circuit

Phase noise and jitter are two indexes to evaluate the performance of periodic signal .This paper introduces the conceptions of phase noise and jitter ,analyzes the relation between them in de‐tail ,designs a clock module with standard low‐jitter frequency .The test result indicates that the root mean square (RMS) periodic jitter isn't more than 250fs .