低抖动时钟产生电路设计 |
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引用本文: | 江平,叶宝盛. 低抖动时钟产生电路设计[J]. 舰船电子对抗, 2016, 0(5): 117-120. DOI: 10.16426/j.cnki.jcdzdk.2016.05.029 |
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作者姓名: | 江平 叶宝盛 |
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作者单位: | 中国电子科技集团公司电子第36研究所,嘉兴,314033 |
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摘 要: | 相位噪声和抖动是考量周期信号性能最常用的2个指标。介绍了相位噪声和抖动的概念,详细分析了两者之间的联系,设计了一个低抖动的标频时钟模块,测试结果表明均方根(RMS)周期抖动≤250 fs。
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关 键 词: | 时钟模块 相位噪声 抖动 |
Design of Low-jitter Clock Generation Circuit |
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Abstract: | Phase noise and jitter are two indexes to evaluate the performance of periodic signal .This paper introduces the conceptions of phase noise and jitter ,analyzes the relation between them in de‐tail ,designs a clock module with standard low‐jitter frequency .The test result indicates that the root mean square (RMS) periodic jitter isn't more than 250fs . |
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Keywords: | clock module phase noise jitter |
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