CRC5/16编码校验模块的FPGA一体化设计

在数字通信领域,为保证数据的正确传输,数据校验是必不可少的,而循环冗余校验(CyclicRedundancy Check,简称CRC)在其中得到广泛的应用。该文首先对CRC5/16校验的基本原理作了简要的介绍,然后对CRC5/16编码校验的具体电路及其实现步骤进行了详尽的阐述。在分析它们实现电路的基础上,提出了将CRC5/16的编码校验放在一个模块中实现的方法,这样不仅节省了硬件资源,而且系统的模块化设计也有利于模块的重复利用与移植。最后给出了在FPGA中的具体实现方法,并利用软件工具及硬件电路对该设计进行了较为全面的仿真验证。

Integration Design of CRC5/16' Codec in FPGA

Cyclic Redundancy Check （CRC for short） is one of the data checkout way widely used in the digital communication system.This paper first simply introduces the basic principle of CRC5/16,then provides the CRC5/16＇s implementation circuits and the steps to use them, Based on these analysis,the paper puts forward the idea that combines the CRC5 and CRC16＇s code and checkout module in a sin-gle one,which not only saves hardware resources,but also provides an easy way to reuse and trans-plante for other design.At last,we give specific implementation in FPGA,and show the result of relatively overall simulation of the design using software and hardware.