| FPGA设计中的亚稳态及其缓解措施 |
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| 引用本文： | 汪路元.FPGA设计中的亚稳态及其缓解措施[J].电子技术应用,2012,38(8). |
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| 作者姓名： | 汪路元 |
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| 作者单位： | 北京空间飞行器总体设计部,北京,100094 |
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| 摘 要： | 亚稳态是异步数字电路设计中的固有现象。针对FPGA产品研制中的亚稳态问题,分析了其产生的原因,阐述了亚稳态对系统可靠性的影响和评估方法,并针对单比特异步传输、多比特异步传输和复位三种情况下的亚稳态提出缓解措施。该措施可以在工程实践中参考使用。
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| 关 键 词： | 触发器 亚稳态 MTBF 复位 |
Metastable state and mitigation measures in FPGA design |
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| Wang Luyuan.Metastable state and mitigation measures in FPGA design[J].Application of Electronic Technique,2012,38(8). |
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| Authors: | Wang Luyuan |
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| Abstract: | Metastable state is inherent in asynchronous digital circuits.This paper introduces the metastable state in FPGA design and analyses the effect on system reliability.Finally,several approaches that can be used in project are discussed to mitigate the effect in the process of one bit or many bits asynchronous transmission or reset. |
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| Keywords: | flip-flop metastable state MTBF reset |
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