A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques |
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Authors: | Honda K Furuta M Kawahito S |
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Affiliation: | Res. Inst. of Electron., Shizuoka Univ., Hamamatsu; |
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Abstract: | This paper presents a low-power low-voltage 10-bit 100-MSample/s pipeline analog-to-digital converter (ADC) using capacitance coupling techniques. A capacitance coupling sample-and-hold stage achieves high SFDR with 1.0-V supply voltage at a high sampling rate. A capacitance coupling folded-cascode amplifier effectively saves the power consumption of the gain stages of the ADC in a 90-nm digital CMOS technology. The SNDR and the SFDR are 55.3 dB and 71.5 dB, respectively, and the power consumption is 33 mW |
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