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三维圆柱形电荷俘获存储器件的继续微缩对其性能的影响
引用本文:李新开,霍宗亮,靳磊,姜丹丹,洪培真,徐强,唐兆云,李春龙,叶甜春. 三维圆柱形电荷俘获存储器件的继续微缩对其性能的影响[J]. 半导体学报, 2015, 36(9): 094008-6. DOI: 10.1088/1674-4926/36/9/094008
作者姓名:李新开  霍宗亮  靳磊  姜丹丹  洪培真  徐强  唐兆云  李春龙  叶甜春
摘    要:本文详细地研究了关键尺寸的继续微缩对三维圆柱形无结型电荷俘获存储器器件性能的影响。通过Sentaurus三维器件仿真器,我们对器件性能的主要评价指标进行了系统地研究,包括编程擦除速度和高温下的纵向电荷损失及横向电荷扩散。沟道半径的继续微缩有利于操作速度的提升,但使得纵向电荷损失, 尤其是通过阻挡层的纵向电荷损失,变得越来越严重。栅极长度的继续微缩在降低操作速度的同时将导致俘获电荷有更为严重的横向扩散。栅间长度的继续微缩对于邻近器件之间的相互干扰有决定性作用,对于特定的工作温度及条件其值需谨慎优化。此外,栅堆栈的形状也是影响电荷横向扩散特性的重要因素。研究结果为高密度及高可靠性三维集成优化提供了指导作用。

关 键 词:3D charge trapping devices  vertical charge loss  lateral charge migration  semiconductor device simulation
收稿时间:2015-01-07
修稿时间:2015-03-07

Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory
Li Xinkai,Huo Zongliang,Jin Lei,Jiang Dandan,Hong Peizhen,Xu Qiang,Tang Zhaoyun,Li Chunlong and Ye Tianchun. Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory[J]. Chinese Journal of Semiconductors, 2015, 36(9): 094008-6. DOI: 10.1088/1674-4926/36/9/094008
Authors:Li Xinkai  Huo Zongliang  Jin Lei  Jiang Dandan  Hong Peizhen  Xu Qiang  Tang Zhaoyun  Li Chunlong  Ye Tianchun
Affiliation:Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Abstract:This work presents a comprehensive analysis of 3D cylindrical junction-less charge trapping memory device performance regarding continuous scaling of the structure dimensions. The key device performance, such as program/erase speed, vertical charge loss, and lateral charge migration under high temperature are intensively studied using the Sentaurus 3D device simulator. Although scaling of channel radius is beneficial for operation speed improvement, it leads to a retention challenge due to vertical leakage, especially enhanced charge loss through TPO. Scaling of gate length not only decreases the program/erase speed but also leads to worse lateral charge migration. Scaling of spacer length is critical for the interference of adjacent cells and should be carefully optimized according to specific cell operation conditions. The gate stack shape is also found to be an important factor affecting the lateral charge migration. Our results provide guidance for high density and high reliability 3D CTM integration.
Keywords:3D charge trapping devices  vertical charge loss  lateral charge migration  semiconductor device simulation
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