Fast adders using enhanced multiple-output domino logic |
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Authors: | Zhongde Wang Jullien G.A. Miller W.C. Jinghong Wang Bizzan S.S. |
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Affiliation: | VLSI Res. Group, Windsor Univ., Ont.; |
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Abstract: | Using an enhanced multiple output domino logic (EMODL) implementation of a carry lookahead adder (CLA), sums of several consecutive bits can be built in one nFET tree with a single carry-in. Based on this result, a new sparse carry chain architecture is proposed for the CLA adder. We demonstrate the design approach using a 32-b adder, and show that only four carries are sufficient for generating all sums, with a consequent reduction in the number of stage delays. Using a 1.2-μm CMOS technology, we verify our simulation procedures by fabrication and measurement of a 2.7 ns critical path |
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