| 基于FPGA的逻辑分析仪的设计 |
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| 引用本文： | 谢维达,刘宜璟. 基于FPGA的逻辑分析仪的设计[J]. 计算机测量与控制, 2005, 13(5): 506-508 |
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| 作者姓名： | 谢维达 刘宜璟 |
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| 作者单位： | 同济大学,铁道与城市轨道交通研究院,上海,200331;同济大学,信息与控制工程系,上海,200331 |
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| 摘 要： | 介绍了一种用FPGA构成的信号处理装置，该装置和计算机结合使用可以实现数字和模拟混合信号的逻辑分析。文章给出了该装置的设计方案和具体实现方法。这种方法将FPGA的特点与PC的特点结合在一起，具有一定的实用性。实践证明这种方案性能在中低速系统应用中优于普通示波器，且其性价比优于普通逻辑分析仪。该装置可以作为逻辑分析仪使用。
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| 关 键 词： | FPGA 逻辑分析仪 Verilog HDL语言 |
| 文章编号： | 1671-4598(2005)05-0506-02 |
| 修稿时间： | 2004-09-03 |
Logic Analyzer Design Based on FPGA |
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| Xie Weida,Liu Yijing. Logic Analyzer Design Based on FPGA[J]. Computer Measurement & Control, 2005, 13(5): 506-508 |
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| Authors: | Xie Weida Liu Yijing |
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| Affiliation: | Xie Weida 1,Liu Yijing 2 |
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| Abstract: | An instrument using the technology of FPGA and the computer which can analyze the logic of a digital-analog mixed signal system is introduced. The architecture of the instrument and the way to implement it are discussed. This instrument has a good practicability since it integrates the features of FPGA and personal computer. It has been proven in the practice that the performance of this instrument is better than the general oscillograph's in the medium or low frequency condition and the cost performance of this instrument is better than the general logic analyzer's. It can be used as the general logic analyzer. |
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| Keywords: | FPGA logic analyzer Verilog HDL |
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