Design and implementation of a new four-quadrant MOS analog multiplier |
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Authors: | C. W. Kim S. P. Park |
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Affiliation: | (1) Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Cheongryang, Seoul, Korea |
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Abstract: | A four-quadrant MOS analog multiplier is proposed using the quarter-square technique, which is based on the quadratic characteristics of an MOS transistor operating in the saturation region and the difference operation of four identical sourced-coupled differential amplifiers. The multiplier has a simple configuration and a large dynamic range over a wide frequency range, since each input signal passes only one transistor to reach the output. The operation of the multiplier was analyzed in detail, and the second-order effects were also analyzed. The proposed circuit was fabricated in 12-V p-well CMOS process with a 5-m minimum feature. The measured results show that linearity error is less than 1% for 5-Vp-p input at ±5 V supply voltage, and the-3 db bandwidth is 30 MHz. |
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