VLSI circuit reconstruction from mask topology |
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| Authors: | NP van der Meijs JT Fokkema |
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| Affiliation: | Laboratory for Network Theory, Department of Electrical Engineering, Delft University of Technology, 2600 GA Delft, The Netherlands;Section of Technical Geophysics, Department of Mining Engineering, Delft University of Technology, 2600 GA Delft, The Netherlands |
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| Abstract: | This paper discusses whether and how parasitic circuit elements must be included in the circuit simulator source file to obtain reliable simulation results. In particular, attention is paid to fabrication tolerances, wire capacitance (including fringing effects), wire resistance (dispersive line effects), coupling capacitances and capacitances associated with contacts and the aspect ratio of (non-rectangular) transistors. |
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| Keywords: | Parasitic circuit elements wire capacitance fringing capacitance coupling capacitance wire resistance dispersive line effects transistor aspect ratio |
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