Optimization of programmable logic arrays |
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Authors: | Rudolf H. Mak |
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Affiliation: | Department of Mathematics and Computing Science, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven, The Netherlands |
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Abstract: | We describe two techniques for the minimization of the area of a Programmable Logic Array (PLA). Based on the logic functions to be implemented an assignment of the inputs and outputs to the columns of a PLA is determined that is especially suited for row segmentation. An upper bound and a lower bound for the number of rows in the segmented PLA are derived. Furthermore, it is shown how the result can be improved upon by the duplication of some of the inputs. |
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Keywords: | Combinational logic area minimization programmable logic arrays array segmentation array folding |
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