多核处理器非一致Cache体系结构延迟优化技术研究综述

非一致Cache体系结构(non-uniform cache architecture,NUCA)为解决多核处理器(chip multi-processor)"存储墙"难题提供了新的设计思路.重点关注面向CMP的NUCA延迟优化技术,在介绍若干典型NUCA模型的基础上,分析大容量Cache环境下共享/私有机制中的延迟-容量权衡问题,讨论映射、迁移、复制和搜索等数据管理机制在多核环境下的优缺点.最后,针对基于片上网络(network-on-chip,NoC)互连结构的可扩展CMP体系结构,从NUCA模型优化、数据管理和一致性维护机制3个方面讨论和预测未来CMP NUCA延迟优化领域的发展趋势及面临的挑战性问题.

Latency Optimization Techniques in Non-Uniform Cache Architecture for Chip Multi-Processors: A Survey

Non-Uniform Cache Architecture (NUCA) provides a new opportunity in solving the "Memory Wall" problem of Chip Multiprocessor (CMP). This survey focuses on the latency reduction techniques of NUCA for CMP. Based on the introduction of several typical models of NUCA for CMP, the trade-off between latency and capacity is analyzed in shared and private mechanism. Furthermore, the advantage and disadvantage of data mechanism is discussed in detail from the perspective of data mapping, migration, replication and search, respectively. Finally, confronted with challenges and opportunities, several open problems about latency reduction techniques aimed at the scalable CMP architecture based on Network-on-Chip (NoC) are explored and predicted from three aspects, such as optimization of NUCA model, data management policy and coherence maintain mechanism.