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System Level Modeling of Microsystems Using Order Reduction Methods |
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| Authors: | Sven Reitz Jens Bastian Joachim Haase Peter Schneider Peter Schwarz |
| Affiliation: | (1) Linköping Design Center, Ericsson Microelectronics AB, Linköping University, Box 1544, SE-581 15, Department of Electrical Engineering, SE-581 83 Linköping, Sweden;(2) Department of Electrical Engineering, Linköping University, SE-581 83 Linköping, Sweden;(3) Department of Electrical Engineering, Linköping University, SE-581 83 Linköping, Sweden;(4) Ericsson Microelectronics, Westmead Dr., Swindon Design Centre, Swindon, SN5 7UN, United Kingdom |
| Abstract: | The dynamic element matching (DEM) techniques for digital-to-analog converters(DACs) has been suggested as a promising method to improve matching between the DAC's referencelevels. However, no work has so far taken the dynamic effects that limit the performance for higher frequenciesinto account. In this paper we present a model describing the dynamic properties of a DEM DAC and compare thesimulated results with measurements of a 14-bit current-steering DEM DAC implemented in a 0.35- m CMOSprocess. The measured data agrees well with the results predicted by the used model. It is also shown that theDEM technique does not necessarily increase the performance of a DAC when dynamic errors are dominating theachievable performance. |
| Keywords: | DAC DEM CMOS matching current-steering |
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