Testability Properties of Divergent Trees |
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Authors: | R.D. Blanton John P. Hayes |
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Affiliation: | (1) Center for Electronic Design Automation, ECE Department, Carnegie Mellon University, Pittsburgh, PA, 15213-3890;(2) Advanced Computer Architecture Laboratory, EECS Department, University of Michigan, Ann Arbor, MI 48109-2122 |
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Abstract: | The testability of a class of regular circuits calleddivergent trees is investigated under a functional fault model. Divergent trees include such practical circuits as decoders anddemultiplexers. We prove that uncontrolled divergent trees aretestable with a fixed number of test patterns (C-testable) if andonly if the module function is surjective. Testable controlled treesare also surjective but require sensitizing vectors for errorpropagation. We derive the conditions for testing controlleddivergent trees with a test set whose size is proportional to thenumber of levels p found in the tree (L-testability). By viewing a tree as overlapping arrays of various types, we also deriveconditions for a controlled divergent tree to be C-testable. Typicaldecoders/demultiplexers are shown to only partially satisfy L- andC-testability conditions but a design modification that ensuresL-testability is demonstrated. |
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Keywords: | fault detection fault modeling regular circuits interactive logic arrays structured circuits test generation |
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