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一种Bipolar结构中的闩锁效应
引用本文:周烨,李冰.一种Bipolar结构中的闩锁效应[J].电子与封装,2009,9(1):20-23.
作者姓名:周烨  李冰
作者单位:无锡硅动力微电子股份有限公司研发中心,无锡,214028
摘    要:闩锁是集成电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致整个器件失效。文章较为详细地阐述了一种Bipolar结构中常见的闩锁效应,并和常见CMOS结构中的闩锁效应做了对比。分析了该闩锁效应的产生机理,提取了用于分析闩锁效应的等效模型,给出了产生闩锁效应的必要条件与闩锁的触发方式。通过对这些条件的分析表明,只要让Bipolar结构工作在安全区,此类闩锁效应是可以避免的。这可以通过版图设计和工艺技术来实现。文章最后给出了防止闩锁效应的关键设计技术。

关 键 词:闩锁效应  寄生晶体管  器件模型  版图设计

A Latch-up in Bipolar Circuit
ZHOU Ye,LI Bing.A Latch-up in Bipolar Circuit[J].Electronics & Packaging,2009,9(1):20-23.
Authors:ZHOU Ye  LI Bing
Affiliation:ZHOU Ye,LI Bing (Wuxi Si-power Micro-Electronics CO.,LTD,Research&Development Center,Wuxi 214028,China)
Abstract:Latch-up is a parasitic effect in CMOS circuits. Once the PNPN structure is triggered, there will be high current from VDD to GND, which makes the chip invalidation. This paper reports that the latch-up occurred in Bipolar circuit structure, which is different from a latch-up in Buck CMOS. The reasons are analyzed; the lumped component model, which is used for analyzing the latch-up, is extracted, and the necessary conditions and the trigger mode of the latch-up are given. It is also indicated, based on ana...
Keywords:latch-up  parasitical transistor  component model  layout design  
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