| BWDSP100数字信号处理器的指令缓存器设计 |
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| 引用本文： | 刘小明,朱艳.BWDSP100数字信号处理器的指令缓存器设计[J].中国集成电路,2013,22(4):48-50,56. |
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| 作者姓名： | 刘小明 朱艳 |
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| 作者单位： | 中国电子科技集团公司第38研究所,安徽合肥,230031 |
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| 摘 要： | 本文介绍了一种应用于高性能数字信号处理器BWDSP100的指令缓存器。该指令缓存器支持超长指令字,共有三级缓冲,每级缓冲包含16个指令槽。该指令缓存器可高效完成指令执行行的提取、拼接及废弃等操作,可有效提高DSP的指令执行效率。
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| 关 键 词： | 数字信号处理器 指令缓存器 超长指令字 |
Instruction alignment Buffer designment of BWDSP1O0 |
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| LIU Xiao-ming
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ZHU Yan.Instruction alignment Buffer designment of BWDSP1O0[J].China Integrated Circuit,2013,22(4):48-50,56. |
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| Authors: | LIU Xiao-ming ZHU Yan |
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| Affiliation: | (No.38th Research Institute,China Electronic Technology Group Corporation,Hefei,230031,China) |
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| Abstract: | This paper introduces a type of Instruclion Alignment Buffer （ IAB ） which has been applied to BWDSP100, a high-performance Digital Signal Processor （ DSP ）.The IAB supports Very-Long Instruction Word （ VLIW ） architecture. It is composed of 3 layers of troffer, and each layer contains 16 instruction slots. The IAB is able to efficiently perform operations of instruction executable lines such as reich, coalesce, dispose, etc.. and improve the efficiency of instruction executions. |
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| Keywords: | Digital Signal Processor （ DSP ） Instruction Alignment Buffer Very-Long Instruction Word （ VLIW ） |
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