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The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide
Authors:Hong Wu  Weifeng Sun  Yangbo Yi  Haisong Li  Longxing Shi
Affiliation:1. College of Communication Engineering, Chongqing University, Chongqing 400044, China;2. National Laboratory of Analogue Integrated Circuits, No. 24 Research Institute of China Electronics Technology Group Corporation, Chongqing 400060, China;1. Christian Doppler Laboratory at the Institute for Microelectronics, Technische Universität Wien, 1040 Vienna, Austria;2. Institute for Microelectronics, Technische Universität Wien, 1040 Vienna, Austria;3. Ioffe Physical-Technical Institute, 194021 St. Petersburg, Russia;4. ams AG, 8141 Unterpremstätten, Austria;1. Corporate Reliability Department, Infineon Technologies AG, D-85579 Munich, Germany;2. Technologies Development Department, Infineon Technologies Dresden GmbH, 01099 Dresden, Germany
Abstract:The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.
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