Signal probability for reliability evaluation of logic circuits |
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| Authors: | Denis Teixeira Franco Maí Correia Vasconcelos Lirida Naviner Jean-François Naviner |
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| Affiliation: | 1. Institut TELECOM, Télécom-ParisTech, LTCI-CNRS, COMELEC Departement, 46 Rue Barrault, 75013 Paris, France;2. Fundação Universidade Federal do Rio Grande, FURG, Rio Grande, RS, Brazil;1. IMEC, Kapeldreef 75, Leuven B-3001, Belgium;2. University of Twente, Postbus 217, Enschede, 7500 AE, Netherlands;3. FB 2.047, NXP Semiconductors, Gerstweg 2, Nijmegen, 6534 AE, Netherlands;1. College of Computer Science and Technology, Zhejiang University of Technology, Hangzhou 310023, China;2. School of Software Engineering, Tongji University, Shanghai 201804, China;1. University of Beira Interior, R. Fonte do Lameiro, Covilha, Portugal;2. INESC-ID, R. Alves Redol, Lisbon, Portugal;3. IST, University of Lisbon, Av. Rovisco Pais, Lisbon, Portugal |
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| Abstract: | As integrated circuits scale down into nanometer dimensions, a great reduction on the reliability of combinational blocks is expected. This way, the susceptibility of circuits to intermittent and transient faults is becoming a key parameter in the evaluation of logic circuits, and fast and accurate ways of reliability analysis must be developed. This paper presents a reliability analysis methodology based on signal probability, which is of straightforward application and can be easily integrated in the design flow. The proposed methodology computes circuit’s signal reliability as a function of its logical masking capabilities, concerning multiple simultaneous faults occurrence. |
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