| VLIW处理器系统级验证平台的设计与实现 |
| |
| 引用本文： | 杨焱,侯朝焕.VLIW处理器系统级验证平台的设计与实现[J].电子测量与仪器学报,2007,21(2):81-85. |
| |
| 作者姓名： | 杨焱 侯朝焕 |
| |
| 作者单位： | 1. 北京交通大学轨道交通控制与安全国家重点实验室,北京,100044
2. 中国科学院声学所,北京,100080 |
| |
| 基金项目： | 本项目为国家重点基础研究发展规划“973”资助项目（编号：G1999032901）. |
| |
| 摘 要： | 本文提出了一种新的VLIW处理器验证平台的实现方法。采用寄存器跟踪技术，建立了一个与RTL模型一致的抽象功能验证模型，基于VXI总线测试技术，实现了高度集成化的系统芯片验证平台，弥补了单一验证技术的不足，设计期功能仿真满足测试覆盖率的要求，并与板级功能测试仿真保持一致，充分证明了方法的有效性。
|
| 关 键 词： | 功能验证 VLIW处理器 寄存器跟踪 测试 |
| 修稿时间： | 2006-03 |
Design and Implementation of VLIW Processor System Level Verification Platform |
| |
| Yang Yan,Hou Chaohuan.Design and Implementation of VLIW Processor System Level Verification Platform[J].Journal of Electronic Measurement and Instrument,2007,21(2):81-85. |
| |
| Authors: | Yang Yan Hou Chaohuan |
| |
| Affiliation: | 1. State Key of Rail Traffic Control and Safety Laboratory, Beijing Jiaotong University, Beijing 100044, China; 2. Institute of Acoustics, Chinese Academy of Sciences, Beijing 100080, China |
| |
| Abstract: | A new function verification model of VLIW processor is presented in this paper to deal with the limitation of conventional verification methods. An abstract verification model in accordance with RTL model was established, and we designed a technology of processor register tracing to speed up functional verification. Using VXI bus technique, an integrated system level verification platform was successfully implemented by combining verification model and design schedule. Chip-level functional simulation demonstrates that this method can cover all areas in the design and verification, improve traditional technology, and meet the demand of function test coverage efficiently. Finally, coincident results for design phase test and post circuit test are achieved, which proves the effectiveness of the method. |
| |
| Keywords: | functional verification VLIW processor register tracing test |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
