| 用Verilog HDL实现基于FPGA的通用分频器的设计 |
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| 引用本文： | 罗浩,;许艳,;仲佳嘉. 用Verilog HDL实现基于FPGA的通用分频器的设计[J]. 适用技术之窗, 2008, 0(10): 215-216 |
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| 作者姓名： | 罗浩, 许艳, 仲佳嘉 |
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| 作者单位： | [1]江西理工大学应用科学学院,江西赣州341000; [2]武汉理工大学信息学院,湖北武汉430070; [3]江西赣州供电公司通信自动化分公司,江西赣州341000 |
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| 摘 要： | 在数字逻辑电路设计中，常常遇到一些对时钟分频的需求。本文实现了一种基于FPGA的软件化的分频方法，通过对不同的Verilog HDL语言程序语句进行比较分析和仿真综合。
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| 关 键 词： | 数字逻辑电路设计 分频器 FPGA Verilog HDL |
Design of General Frequency Divider Based on FPGA Using Verilog HDL |
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| Affiliation: | Luo Hao Xu Yan Zhong Jiajia(1.College of Applied Science, Jiangxi Univ. of Science ＆ Technology, Jiangxi Ganzhou 341000; 2. School of Information Engineering, Wuhan Univ. of Technology, Hubei Wuhan 430070;3. Branch of Communication and Automatization, Jiangxi Ganzhou Electric Power Corporation, Jiangxi Ganzhou 341000) |
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| Abstract: | Due go the limitation of the frequency dividers recently widely used, in this paper, a new software method of frequency dividers based on FPGA is introduced. Comparison and analysis are presented, and synthesis and simulation are performed by different Verilog HDL language program statement. |
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| Keywords: | Digital Logic Circuit Design Frequency Divider FPGA Verilog HDL |
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