一款低抖动宽调节范围锁相环频率合成器的设计

提出了一种基于SMIC公司0.18μm工艺、输出频率范围为1 GHz～3 GHz的低抖动电荷泵锁相环频率合成器设计方法.该设计方法采用一种新型自动调节复位脉冲的鉴频鉴相器结构,可以根据压控振荡器反馈频率自动调节不同的脉冲宽度,用以适应不同的输出时钟.仿真结果显示该器件能够有效降低锁相环频率合成器的抖动,其最大峰-峰值抖动为20.337 ps,锁定时间为0.8μs,功耗为19.8 mW.

A Design of Low-Jitter and Wide Tuning Range PLL Frequency Synthesizer

A low-jitter and wide tuning range Phase Locked Loop （PLL） Frequency Synthesizer is de- signed based on 0.18 μm CMOS Process with an output range of 1 GHz to 3 GHz. A new Phase/Fre- quency detector （PFD） structure with capability of self-adjusting the widths of reset pulses is introduced to automatically-adjust widths of different pulses according to the feedback frequency of VCO. Simulation results show that the jitter of PLL Frequency Synthesizer is suppressed effectively. The PLL Frequency synthesizer has a maximum peak to peak jitter of 20.337 ps, a lock time of 0. 8 ＇s and a power consump- tion of 19.8 roW.