Optimization of a self-aligned titanium silicide process forsubmicron technology |
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| Authors: | Levy D. Delpech P. Paoli M. Masurel C. Vernet M. Brun N. Jeanne J.-P. Gonchond J.-P. Ada-Hanifi M. Haond M. D'Ouville T.T. Mingam H. |
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| Affiliation: | Bull, Les Clayes-sous-Bois; |
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| Abstract: | The optimization of a manufacturable self-aligned titanium silicide process is described. In particular, the integrity of the TiSi 2 layer has been studied versus the BPSG reflow conditions. Excellent contact resistance and very low leakage currents have been obtained. The good device parameters obtained with an n+ or n +/p+ gate have demonstrated that the self-aligned process can be integrated in a 0.8-μm double-metal CMOS process |
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