Novel FPGA implementations of Walsh-Hadamard transforms for signalprocessing |
| |
Authors: | Amira A Bouridane A Milligan P Roula M |
| |
Affiliation: | Sch. of Computer. Sci., Queen's Univ., Belfast ; |
| |
Abstract: | The paper describes two approaches suitable for a field-programmable gate-array (FPGA) implementation of fast Walsh-Hadamard transforms. These transforms are important in many signal-processing applications including speech compression, filtering and coding. Two novel architectures for the fast Hadamard transforms using both a systolic architecture and distributed arithmetic techniques are presented. The first approach uses the Baugh-Wooley multiplication algorithm for a systolic architecture implementation. The second approach is based on both a distributed arithmetic ROM and accumulator structure, and a sparse matrix-factorisation technique. Implementations of the algorithms on a Xilinx FPGA board are described. The distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach |
| |
Keywords: | |
|
|