A low-power phase-locked loop for UWB applications |
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Authors: | Tapio Rapinoja Kari Stadius Kari Halonen |
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Affiliation: | (1) Electronic Circuit Design Laboratory, Helsinki University of Technology, P.O. Box 3000, 02015 TKK Espoo, Finland |
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Abstract: | This paper describes a low-power phase-locked loop (PLL) design for WiMedia UWB synthesizer implemented in a 0.13-μm CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of −54 dBc and in-band phase noise of −78 dBc/Hz. |
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