基于DSP的ADC测试功耗优化设计

随着大规模混合信号集成电路设计水平及复杂性的不断提高,对其进行测试的难度与成本变得越来越高,而测试功耗过高已经成为影响测试成本的一个重要因素。ADC作为混合信号电路的典型代表,已经应用在了各种集成模块上。文章中为降低ADC测试功耗,对ADC的测试结构进行了部分改进,并运用遗传算法搜索了低功耗测试激励。理论研究及仿真实验表明,优化后的结构和低功耗测试激励较优化前能同时降低测试时的峰值功耗和平均功耗。

Power optimization and structural design of DSP-based ADC testing

With the continuous improvement of designing standards and complexity of large-scale mixed-signal integrated circuits,the test difficulty and test cost is becoming increasingly higher.The too higher test power consumption has become an important factor of test cost.ADC,as a typical representative of the mixed-signal circuits,has been applied in a variety of integrated modules.In order to reduce the ADC test power consumption,this article has done some improvement on the ADC test structure,and,using the genetic algorithms to searched low power consumption test stimulus.Theoretical studies and simulation results show that,compared with the original structure,the low-power test stimulus can simultaneously reduce test peak power and average power consumption.