| 基于VHDL和CPLD的协调控制器系统总线桥 |
| |
| 引用本文： | 袁朝辉,朱伟,徐鹏. 基于VHDL和CPLD的协调控制器系统总线桥[J]. 微处理机, 2005, 26(4): 79-81,85 |
| |
| 作者姓名： | 袁朝辉 朱伟 徐鹏 |
| |
| 作者单位： | 西北工业大学自动化学院,西安,710072 |
| |
| 摘 要： | 本文介绍了一种使用VHDL语言设计、在一片EMP7128S160 CPLD芯片上实现的总线桥。该总线桥是某型协调控制器系统的通讯核心，实现了系统下层的背板总线、背板总线管理器与上位机EPP并口之间的协议转换以及通讯仲裁功能。该桥为系统下层提供了高速的实时数据传输通道，也为上位机访问下层系统提供了完全的访问通道，使整套控制器兼具高性能、易调试两大特点。
|
| 关 键 词： | VHDL CPLD 协调控制器 总线桥 EPP并口 |
| 文章编号： | 1002-2279（2005）04-0079-03 |
| 收稿时间： | 2004-10-29 |
| 修稿时间： | 2004-10-29 |
Bus- Bridge Based on VHDL and CPLD Used in a Kind of Harmony Control System |
| |
| YUAN Zhao-hui,ZHU Wei,XU Peng. Bus- Bridge Based on VHDL and CPLD Used in a Kind of Harmony Control System[J]. Microprocessors, 2005, 26(4): 79-81,85 |
| |
| Authors: | YUAN Zhao-hui ZHU Wei XU Peng |
| |
| Abstract: | A bus-birdge, based on VHDL and CPLD, used in a kind of harmony controller system,was introduced in this paper.This bridge is the core of communication of the controller system, it connects the bottom level backplane bus, backplane bus controller, and PC EPP parallel port. With this bridge, the bottom part of the controller system achieves high real-time performance, and the top level ( PC) achieves full access to the bottom part, which provide great convenience in system debugging and high flexibility in application. |
| |
| Keywords: | VHDL CPLD Harmony Controller System Bus - Bridge EPP parallel port |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
