存储阵列中的串扰分析及脉冲产生电路设计

在SRAM存储阵列的设计中,经常会遇到相邻信号线与电路节点间耦合引起的串扰问题。针对这个问题给出位线“间隔译码”的组织结构,有效地降低了存储器读写时寄生RC所带来的串扰。同时,针对该“间隔译码”的存储阵列结构,设计了脉冲产生电路,该电路只需要利用行地址的变化来生成充电脉冲,不仅简化了电路的规模,而且减小了读写操作时存储阵列中单元之间的串扰,提高了可靠性。

Analysis of Cross Talk in Memory Array and Design of Pulse Generator Circuit

In the design of SRAM memory array,we often meet with the problem about cross talk which is brought about by adjacent signal wire and node coupling.In this paper,we discuss a new memory array-interval decoding architecture,which decreases cross talk parasitical RC aroused effectively during the period of read and writing operation.Simultaneously,we devise a pulse generator circuit,which produces charge-pulse by changing row address.The circuit not only simplifies the size,but also lower cross talk among memory array,which improves the reliability.