Floorplan design of VLSI circuits

In this paper we present two algorithms for the floorplan design problem. The algorithms are quite similar in spirit. They both use Polish expressions to represent floorplans and employ the search method of simulated annealing. The first algorithm is for the case where all modules are rectangular, and the second one is for the case where the modules are either rectangular or L-shaped. Our algorithms consider simultaneously the interconnection information as well as the area and shape information for the modules. Experimental results indicate that our algorithms perform well for many test problems.This work was partially supported by the Semiconductor Research Corporation under Contract 86-12-109, by the National Science Foundation under Grant MIP 8703273, and by a grant from the General Electric Company.