三维IP核绑定前后总测试时间的优化方法

为了减少三维IP（Intellectual Property）核绑定前和绑定后的测试总时间，提出了一种测试外壳扫描链优化方法。方法首先将三维IP核的所有扫描元素投影到一个平面上，用BFD算法将扫描元素分配到各条测试外壳扫描链，以减少绑定后的测试时间。再用提出的AL（Allocate Layer）算法将扫描元素分配到各层电路中，使得绑定前各条测试外壳扫描链的长度也能够平衡，以减少绑定前的测试时间和TSVs数量，并且AL算法能够使得各层电路所含的扫描元素总长度也尽可能的相等。实验结果表明，与国际上已有的方法相比，所提方法绑定前和绑定后的测试总时间减少了3.17%~38.18%，并且三维IP核各层电路所含的扫描元素总长度更加均衡。

Optimizing pre-bond and post-bond test time for three dimension IP cores

To reduce pre-bond and post-bond test time of three dimensional IP（Intellectual Property）cores, this paper proposes a test wrapper optimization technique. The proposed technique maps scan elements to a plane, and BFD algorithm is employed to allocate scan elements to each wrapper chain to reduce post-bond test time. Secondly, AL（Allocate Layer） algorithm is presented to allocate scan elements to each circuit layer to balance pre-bond wrapper chains, which can effectively reduce pre-bond test time and the number of TSVs. Besides, AL algorithm can also make the total length of scan elements in each layer as equal as possible. Experiments show that the proposed technique can further reduce test time by 3.17%~38.18%, and balance the length of total scan elements in each circuit layer of 3D IP core.