基于FPGA的快速连通区域标记算法的设计与实现

针对无行消隐图像不间断输入的高速图像处理情况，提出一种快速连通区域标记算法的硬件实现方法。利用游程编码优化标号生成算法，减小临时标号数量和等价表长度，并可同时完成特征提取；利用逐像素扫描法，以单时钟周期实现标号跟踪；利用等价表合并方法完成标号合并和特征合并。FPGA仿真结果表明：对连续输入的二值图像进行连通区域标记和特征提取时，运行时间仅由图像输入时间和等价表合并时间组成，明显优于其他方法，可适用于图像的快速识别与跟踪。

Design and implementation of fast connected component labeling algorithm based on FPGA

A fast connected component labeling algorithm based on FPGA is presented for high speed image processing on the condition that the images are continuous without horizontal blanking. Using run length code to optimize image labeling, the labels’ number and length of equivalent table can be reduced. And the component’s features can also be extracted during run length coding. Then using the way of scanning every pixel, the connected labels can be linked in a single clock period. Finally the labels and features are merged in the procedure of equivalent table combination. The FPGA simulation results indicate that, when connected component labeling and features extraction for a continuous binary image are in progress, the processing time just includes the image input time and the equivalents table combination time. It is more efficient than others and suitable for fast image recognition and tracking.