| 基于AMBA总线的IIC协议IP核设计与验证 |
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| 引用本文： | 王建雄,肖 明,余 龙.基于AMBA总线的IIC协议IP核设计与验证[J].微处理机,2014(1):4-8. |
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| 作者姓名： | 王建雄 肖 明 余 龙 |
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| 作者单位： | [1]江苏科技大学计算机学院,镇江212003 [2]东莞市泰斗微电子有限公司,东莞523808 |
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| 摘 要： | 介绍了一种基于AMBA总线verilogHDL实现的IIC主机模式的IP核设计。该模块能够在标准和快速模式下运行，能够灵活配置为十位地址寻址或七位地址寻址模式。详细说明了该IP核的架构，各部分设计及状态转换过程。最后该模块通过了系统验证，并在xilinxFPGA上转化为硬件电路实现了所有功能。
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| 关 键 词： | AMBA总线 Verilog HDL语言 IIC协议 IP核 |
Design and Verification of IP Core of IIC Protocol Based on AMBA Bus |
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| WANG Jian - xiong,XIAO Ming,YU Long.Design and Verification of IP Core of IIC Protocol Based on AMBA Bus[J].Microprocessors,2014(1):4-8. |
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| Authors: | WANG Jian - xiong XIAO Ming YU Long |
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| Affiliation: | 1. School of Computer Science, Jiangsu University of Science and Technology, Zhenjiang 212003, China ; 2. Techtotop Micro - electronics Company of Dongguan City, Dongguan 523808, China ) |
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| Abstract: | This article describes an IP core design of IIC master, base on AMBA bus, which implements by verilog HDL. The module can runs in standard mode and quick mode, and it can be flexibly configured to be ten bit or seven bit addressing mode. This article describes the structure of IP core, and its design and status conversion process. Finally, the module has passed the system -level verification and all functions have been implemented in Xilinx FPGA hardware. |
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| Keywords: | AMBA Bus Verilog HDL IIC protocol IP core |
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